IP and Applications Portfolio

BSS owns the IP blocks outlined below, all of which have been successfully integrated and built into the mentioned applications with over 2 million hours of operations.

• STM-n parametrize-able channelized framer (n=1/4/16)
• STM-64 channelized framer
• OTU1 GFEC framer
• OTU1 EFEC framer
• OTU2 GFEC framer
• OTU2 EFEC framer
• 2.5 custom RS FEC
• 2.5G EFEC IP
• 10G GFEC IP
• 10G EFEC i.4/i.7 IP
• Scalable GE L2+ switch
• 1G GFP framer
• 10G GFP framer
• GE/STM-1/STM-4/STM-16 <> OTU2 GFEC/EFEC MuxPonder IP
• GE/STM-1/STM-4 <> OTU1/e GFEC/EFEC IP
• 10GE/STM-64/OTU2 <> OTU4 MuxPonder IP
• 10GE <> OTU2/e Transponder IP (single line or redundant)
• STM-64 <> OTU2/e Transponder IP (Single line or redundant)
• 10GE <> MACSEC encryption IP
• 1G <> MACSEC encryption IP
• 400G transparent clocking switch fabric
• 100G transponder solution.
• QSFP-DD HW, SW and test solution.
• SDK for 400ZR home grown DSP.
• 400G MuxPonder.
• 400G DSP verification architecture
• 400G tester.
• 100G Sniffer.
• 20x10G port OTN ADM
• CFP2 circuit and embedded SW design.
• SFP+ circuit and Embedded SW design.
• Transponder in an SFP+ (MACSEC / OTN )
• 5x7 optical module
• 400G QSFP-DD high Speed transmission line design
• System architecture for the development of 10G switching technology. Responsibilities included crafting detailed architectural specifications for five ASIC devices capable of providing 80G worth of QOS enabled L2/L3/L4 switching and leading a team of 50 engineer that implemented the design successfully.
• Project verification lead for a 16 FPGA 20 MPPS IPV4/MPLS routing engine .